1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which is aimed at forming a three-dimensional structure having a space therein and, more particularly, to a method of manufacturing an infrared image sensor.
2. Description of the Related Art
A description is given of a conventional method of manufacturing a semiconductor device to which the invention relates with reference to a structure of a pixel of an uncooled infrared image sensor as an example. FIG. 14A is a cross sectional view showing a structure of a unit element or a pixel of an uncooled infrared image sensor that is a type disclosed in Japanese Laid-Open Patent Publication 209418/1998 or Proceedings of SPIE, No. 3698, pp. 556-564 in which an infrared ray absorbing portion for absorbing infrared rays to increase the temperature of a photodetector portion and a temperature detecting portion that forms a temperature sensor to detect the temperature rise are formed as separate structures. FIG. 14B is a plane view of the structure shown in FIG. 14A with the infrared ray absorbing portion removed. FIG. 14A is a cross sectional view along the line XIVAxe2x80x94XIVA in FIG. 14B taken before removing the infrared ray absorbing portion.
FIGS. 14A and 14B omit a signal readout circuit which is formed on a silicon substrate 1, as it is not directly related to the invention. In those figures, reference numeral 1 represents a silicon substrate; reference numeral 10 represents a temperature detecting portion which is supported above a hollow portion 200 provided in the silicon substrate 1 with support legs 21 and 22; reference numeral 11 represents a temperature sensor constituted by a bolometer or the like for detecting a temperature change; reference numeral 12 represents an insulating film constituted by a silicon dioxide film or the like that covers the temperature sensor 11; and reference numerals 13 and 14 represent metal wirings for readout of signals from the temperature sensor 11. The support legs 21 and 22 are constituted by insulating films that are silicon dioxide films 23 and 24 similar to that of the temperature detecting portion, and metal wirings 25 and 26 are provided in the insulating films. Reference numeral 130 represents an infrared ray absorbing portion for absorbing infrared rays and converting them into heat, and reference numeral 140 represents a splicing pillar for holding the infrared ray absorbing portion at a certain interval from the temperature detecting portion 10 and for thermally integrating the infrared ray absorbing portion 130 and temperature detecting portion 10. Reference numerals 31 and 32 represent insulating films constituted by silicon dioxide films or the like formed on the substrate 1, and reference numerals 33 and 34 represent metal wirings formed in the insulating films 31 and 32.
An operation of a pixel of the uncooled infrared image sensor will now be described. Infrared rays impinge upon the infrared ray absorbing portion 130. The incident infrared rays are absorbed by the infrared ray absorbing portion 130 to increase the temperature of the infrared ray absorbing portion 130. The temperature change of the infrared ray absorbing portion 130 is conducted to the temperature detecting portion 10 through the splicing pillar 140 to increase the temperature of the temperature detecting portion 10. The splicing pillar 140 is designed such that it has thermal resistance lower than that of the support legs 21 and 22. A time constant determined by the total thermal capacity of the three structures, that is, temperature detecting portion 10, splicing pillar 140 and infrared ray absorbing portion 130, and the thermal resistance of the support legs 21 and 22 is shorter than a frame time during which the uncooled infrared image sensor operates. Since the support legs 21 and 22 are designed such that they have thermal conductance sufficiently lower than that of the splicing pillar 140, the temperature rise at the temperature detecting portion 10 substantially coincides with the temperature rise at the infrared ray absorbing portion 130. It is therefore possible to detect infrared rays by measuring the temperature rise with the temperature sensor 11.
A method of manufacturing the pixel structure shown in FIGS. 14A and 14B will now be with reference to FIGS. 15 through 19.
A signal readout circuit (not shown) is firstly formed on a silicon substrate 1 having a (100)-plane orientation, and an insulating film 2 (which will become insulating films 12, 23, 24, 31 and 32 at the next step), metal wirings 13, 14, 25, 26, 33 and 34 and a temperature sensor 11 are thereafter formed (see FIG. 15).
Subsequently, etching holes 41, 42, 43, and 44 for forming a hollow portion in the silicon substrate 1 are formed by means of etching in the insulating film 2 which is constituted by a silicon dioxide film; a sacrificial layer 110 made of amorphous silicon or the like which is to be removed at a later step is thereafter formed on the wafer; photolithography and etching techniques are then used to form a hole penetrating through the sacrificial layer 110 in a region of the sacrificial layer 110 where a splicing pillar is to be formed; and the hole is filled with a material which will become a splicing pillar 140 (see FIG. 16).
The above-described step separates the insulating film 2 into regions 12, 23, 24, 31 and 32. At this step, it is preferable to flatten the top surface using an etch-back technique, CMP (chemical mechanical polishing) or the like. The splicing pillar 140 may be constituted by the same material that constitutes an infrared ray absorbing portion 130 as disclosed in Japanese Laid-Open Patent Publication 209418/1998, and the infrared ray absorbing portion 130 is formed concurrently with the splicing pillar 140 in this case.
A thin film to become the infrared ray absorbing portion 130 is formed on the sacrificial layer 110 and is patterned into a separated infrared ray absorbing portion for each pixel (see FIG. 17
The sacrificial layer 110 is etched from an opening around the infrared ray absorbing portion 130 to separate the infrared absorbing portion 130 above the substrate 1 with the splicing pillar 140 left between them (see FIG. 18).
The silicon substrate 1 is etched from the exposed regions of the silicon substrate 1 at the bottom of the etching holes 41, 42, 43 and 44. As a result, a hollow portion 200 is formed in the silicon substrate 1 (see FIG. 19).
When the sacrificial layer 110 is formed of amorphous silicon, the sacrificial layer 110 and the silicon substrate 1 can be simultaneously etched. When the silicon is etched using an etchant, such as potassium hydroxide (KOH), tetramethyl ammonium hydroxide (TMAH), or the like, the etching rate decreases as (111)-crystal planes are exposed in so-called anisotropic etching. It is therefore possible to form an etched section having a configuration as shown in FIG. 19 without expanding the surface configuration of the hollow portion 200 beyond a certain size by using a silicon substrate whose surface is a (100)-plane which is commonly used for MOS (metal oxide semiconductor) and CMOS (complimentary metal oxide semiconductor) devices.
While the removal of the sacrificial layer 110 and the formation of the hollow portion 200 in the silicon substrate 1 is carried out using an etchant, that is, using a wet process in the above-described example of the prior art, such a wet process had a possibility of deformation of a constituent part of a pixel attributable to the surface tension of a residue of the liquid on the surface of the pixel structure at the final drying step. For example, there is a high possibility of a problem referred to as xe2x80x9cstickingxe2x80x9d in which the silicon substrate 1 stays in contact with the infrared ray absorbing layer 130 and insulating film 2 that cover the same, and the occurrence of this problem has significantly reduced yield.
As a countermeasure against this, it is preferable to use a dry process, i.e., etching using a gas such as XeF2. Dry etching utilizing an etching gas of this type was isotropic, and the etching gas introduced into the silicon substrate 1 through the etching holes 41 through 44 dry-etched the silicon substrate 1 into a configuration (see FIG. 20).
FIG. 21 is a cross sectional configuration obtained by isotropic dry etching of the structure shown in FIG. 20 in which pixels are two-dimensionally arranged. The arrows in FIG. 21 indicate paths for introduction of an etching gas. As a result of such isotropic etching, the hollow portion 200 in the silicon substrate 1 of each pixel is expanded in the lateral direction and may be connected to the hollow portions of adjacent pixels in the worst case, which has disabled formation of each pixel.
In order to solve such a problem, Japanese Laid-Open Patent Publication 209418/1998 proposed a method in which an etching stopper having a trench structure is formed in a silicon substrate. In this case, however, when etching is performed until the bottom surface of the temperature detecting portion is completely covered by a hollow, a deep etching stopper is required because etching most actively proceeds directly under each of the etching holes to etch the periphery of the hollow portion deeper.
Further, Japanese Laid-Open Patent Publication 209418/1998 disclosed a method in which an etching hole 401 is provided also in the vicinity of the centers of the infrared ray absorbing portion 130 and temperature detecting portion 11 (see FIG. 22). This method also has a problem in that the neighborhood of etching stoppers 301 and 302 is etched deeply because the etching gas is introduced to the peripheral region through the etching holes 41 through 44 to promote etching in that region.
As described above, according to the prior art, when the removal of the sacrificial layer 110 and the formation of the hollow portion 200 in the silicon substrate 1 is carried out using wet etching, sticking can be caused by the surface tension of the liquid that is left on the surface of the pixel structure at the final step of drying the device.
On the other hand, when dry etching is performed using an etching gas such as XeF2, a plurality of regions are etched in association with the positions of etching holes according to the conventional manufacturing method, and the etching most actively proceeds directly under each of the etching holes. This results in a need for limiting the progress of the etching in the lateral direction.
Even when the etching hole 401 that penetrates from the surface through the infrared ray absorbing portion 130, the interior of the splicing pillar 140 and the insulating film 12 is provided to cause dry etching to start at the region directly under the splicing pillar, the dry etching simultaneously proceeds also from the etching holes 41 through 44 in the peripheral region to most actively etch the region directly under each of the etching holes. This results in a need for limiting the progress of the etching in the lateral direction.
Further, since the progress of dry etching may be uneven across a wafer or from wafer to wafer, a deep etching stopper must be provided in sufficient consideration to a margin for manufacture for the purpose of manufacture with high yield. The formation of such a deep etching stopper results in a reduction of yield because of an increase in the etching time attributable to the formation of a deep trench, the difficulty of etching with a high aspect ratio and the difficulty of the formation of an embedded trench that makes it difficult to perform fabrication with high reproducibility.
Further, when the etching rate significantly varies across a wafer or from wafer to wafer, production is quite difficult because a very deep etching stopper is required.
A method of manufacturing a semiconductor device having a plurality of unit element regions according to the invention has the steps of: forming an etching stopper portion embedded in a semiconductor substrate for each unit element region; the etching stopper portion located at a predetermined distance from the center of the unit element region; forming a first structure on a surface of the semiconductor substrate in the unit element region; forming at least one first etching hole in the first structure located in between the neighborhood of center of the first structure and the location of the etching stopper portion, the first etching hole penetrating the first structure to reach the semiconductor substrate; forming a sacrifice layer on the first structure; forming at least one splicing pillar which penetrates the sacrifice layer to reach the first structure; forming a second structure on the sacrifice layer; forming a second etching hole which penetrates the second structure, the splicing pillar and the first structure to reach the semiconductor substrate, the second etching hole being along with the central axis of the splicing pillar; introducing an etching gas through the second etching hole to etch the semiconductor substrate thereby forming a hollow portion which is configured such that it has a largest depth right beneath the splicing pillar, gradually becomes shallower toward the etching stopper portion and has smallest depth where the hollow portion is in contact with the etching stopper portion; sequentially etching the sacrifice layer with the etching gas which is supplied through the first etching hole from the hollow portion concurrently with progress of etching of the semiconductor substrate.
The method may further comprise the steps of: forming a third etching hole whose bottom reaches the sacrifice layer through said infrared absorbing portion; and introducing an etching gas through the second etching hole to etch the semiconductor substrate thereby forming a hollow portion and simultaneously introducing an etching gas through the third etching hole to etch the sacrifice layer.
A method of manufacturing an infrared image sensor having a plurality of unit element regions according to the invention has the steps of: forming an etching stopper portion embedded in a semiconductor substrate for each unit element region, the etching stopper portion located at a predetermined distance from the center of the unit element region; forming an insulating film portion having a metal wiring and a temperature sensor embedded therein, on a surface of the semiconductor substrate in the unit element region; forming at least one first etching hole in the insulating film portion located in between the neighborhood of center of the insulating film portion and the location of the etching stopper portion, the first etching hole penetrating the insulating film portion to reach the semiconductor substrate; forming a sacrifice layer on the insulating film portion; forming at least one splicing pillar which penetrates the sacrifice layer to reach the insulating film portion; forming an infrared absorbing portion on the sacrifice layer; forming a second etching hole which penetrates the infrared absorbing portion, the splicing pillar and the insulating film portion to reach the semiconductor substrate, the second etching hole being along with the central axis of the splicing pillar; introducing an etching gas through the second etching hole to etch the semiconductor substrate thereby forming a hollow portion which is configured such that it has a largest depth right beneath the splicing pillar, gradually becomes shallower toward the etching stopper portion and has smallest depth where the hollow portion is in contact with the etching stopper portion; sequentially etching the sacrifice layer with the etching gas which is supplied through the first etching hole from the hollow portion concurrently with progress of etching of the semiconductor substrate.